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Response time analysis of hard real-time tasks with STM transactions on multi-core platforms
Ref: CISTER-TR-150501       Publication Date: 1, May, 2015

Response time analysis of hard real-time tasks with STM transactions on multi-core platforms

Ref: CISTER-TR-150501       Publication Date: 1, May, 2015

Abstract:
Recent embedded processor architectures integrating multiple heterogeneous cores and non-coherent caches renewed attention to the use of Software Transactional Memory (STM) as a building block for developing parallel applications. STM promises to ease concurrent and parallel software development, but relies on the possibility of abort conflicting transactions to maintain data consistency, which in turns affects the execution time of tasks carrying transactions. The possibility of a transaction abort-and-repeat incurs execution time overheads that have to be accounted for in the WCET of the task that executes the transaction.
In this paper we formalise a response time analysis for sets of non-independent tasks that use STM to share data, and in which transactions are scheduled by following the non-preemptive approaches NPDA, NPUC and the fully preemptive SRP-TM.

Authors:
António Barros
,
Patrick Meumeu Yomsi
,
Luis Miguel Pinho




Record Date: 2, May, 2015