
Duration: 36 months
Country/Territory: France
Within a multidisciplinary technological research team of experts in SW/HW co-design tools by applying formal methods, you will be involved in a national research project aiming at developing an environment to identify, analyze and reduce the interferences generated by the concurrent execution of applications on a heterogeneous commercial-off-the-shelf (COTS) multi-core hardware platform.
Your main missions will be :
1. To propose and develop a formal modeling strategy for the temporal behavior of the hardware platform's microarchitecture and memory hierarchy based on microbenchmarking results of the platform. The microbenchmarking results are produced by a project partner. This modeling will be used to identify interferences and the impact of temporal anomalies on memory accesses, especially their temporal predictability.
2. To propose and develop an approach to make the execution of applications more predictable by reducing the interferences identified in point 1. via the definition of specific rules at the level of their execution model but also at the level of their programming model to guide code synthesis. The whole will be enhanced by the integration of such an approach within a compilation environment chosen by the project partners.
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