Response time analysis of memory-bandwidth- regulated multiframe mixed-criticality systems
Ref: CISTER-TR-211006 Publication Date: 14 to 15, Dec, 2021
Response time analysis of memory-bandwidth- regulated multiframe mixed-criticality systems
Ref: CISTER-TR-211006 Publication Date: 14 to 15, Dec, 2021Abstract:
The multiframe mixed-criticality task model eliminates the pessimism in many
systems where the worst-case execution times (WCETs) of successive jobs vary
greatly by design, in a known pattern. Existing feasibility analysis techniques
for multiframe mixed-criticality tasks are shared-resource-oblivious, hence un-
safe for commercial-o -the-shelf (COTS) multicore platforms with a memory
controller shared among all cores. Conversely, the feasibility analyses that
account for the interference on shared resource(s) in COTS platforms do not
leverage theWCET variation in multiframe tasks. This paper extends the state-
of-the-art by presenting analysis that incorporates the memory access stall in
memory-bandwidth-regulated multiframe mixed-criticality multicore systems.
An exhaustive enumeration approach is proposed for this analysis to further
enhance the schedulability success ratio. The running time of the exhaustive
analysis is improved by proposing a pruning mechanism that eliminates the
combinations of interfering job sequences that subsume others. Experimental
evaluation, using synthetic task sets, demonstrates up to 72% improvement in
terms of schedulability success ratio, compared to frame-agnostic analysis.
Ishfaq Hussain
Muhammad Ali Awan
Pedro Souto
Konstantinos Bletsas
Eduardo TovarDocument:
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DownloadInternational Conference on Embedded Software and Systems (ICESS) (ICESS), Mixed-Criticality Embedded Systems.
Shanghai, Australia.
Record Date: 19, Oct, 2021