Memory Bandwidth Regulation for Multiframe Task Sets
Ref: CISTER-TR-190629 Publication Date: 18 to 21, Aug, 2019
Memory Bandwidth Regulation for Multiframe Task Sets
Ref: CISTER-TR-190629 Publication Date: 18 to 21, Aug, 2019Abstract:
Timing analysis of safety-critical real-time embedded
systems should be free of both optimistic and pessimistic
aspects. The multiframe model was devised to eliminate the
pessimism in the schedulability analysis of systems with tasks
whose worst-case execution times vary from job to job, according
to known patterns. However, this model is optimistic and unsafe
for multicores with shared memory controllers, since it ignores
memory contention, and existing approaches to stall analysis
based on memory regulation are very pessimistic if straightforwardly
applied. This paper remedies this by adapting existing
stall analyses for memory-regulated systems of conventional
Liu-and-Layland tasks to the multiframe model. Experimental
evaluations with synthetic task sets (and different task and
memory budget assignment heuristics) show up to 85% higher
scheduling success ratio for our analysis, compared to the frameagnostic
analysis, enabling higher platform utilisation without
compromising safety. We also explore implementation aspects,
such as how to speed up the analysis and how to trade off
accuracy with tractability.
Muhammad Ali Awan
Pedro F. Souto
Konstantinos Bletsas
Benny Åkesson
Eduardo TovarEvents:
Document:
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Download25th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2019).
Hangzhou, China.
DOI:10.1109/RTCSA.2019.8864563.
ISBN: 978-1-7281-3197-9.
ISSN: 2325-1301.
Record Date: 25, Jun, 2019